The present invention relates to a demodulator for demodulating a quadrature-modulated input signal and more particularly to a demodulator applying a digital signal processing technique.
With the rapid progress of the LSI technology, it has been attempted to apply the digital signal processing technology to demodulators in a field of high-speed communication system with a modulation speed of, for example, 10 MHz. The demodulator applying the digital signal processing technology (hereinafter referred to as a digital demodulator) has a variety of advantages over a demodulator formed of analog circuits. For example, the digital demodulator has no variations in temperature and humidity with elapse of time and thus realizes a stable performance. The digital demodulator can also be fabricated in the form of an LSI. Further, the digital demodulator requires no adjustment and yet allows its specifications to be changed easily.
In order to realize, by the use of the digital signal processing technology, the main functions of the demodulator including a roll-off filter, the sampling rate must be compliant with a sampling theorem. In the theorem, the sampling frequency must be more than two times the maximum frequency component of a signal. That is, if the modulation speed is 10 MHz, the sampling rate needs to be 20 MHz or higher. Similarly, if the modulation speed is 20 MHz, the sampling rate needs to be 40 MHz or higher.
To enable the digital demodulation to be performed at the same speed as this sampling rate, the digital demodulator needs to be constructed of very fast devices and is also required to perform pipeline processing.
However, as the sampling rate is further increased accompanying with an increase in the modulation speed, the operation speed of the devices may not be able to catch up with the increased sampling rate. For example, if the modulation speed exceeds 50 MHz, realizing such devices with the present technology is very difficult.
Further, as the sampling rate increases, the number of pipelining stages also increases. This means an increase in xe2x80x9cdelayxe2x80x9d in the pipeline processing. An increased delay will inevitably enlarge a scale of the circuit and lead to degradation of feedback control characteristics, particularly carrier wave reproduction loop characteristics.
To solve the problem described above, it is an object of the present invention to provide a digital demodulator that can be applied to higher-speed communication systems.
The present invention solves the above problems by carrying out a serial-parallel conversion (S/P conversion) on an A/D-converted signal to make the demodulation speed equal to the modulation speed. In addition, the present invention arranges various components performing the digital demodulation processing in such a way that they can perform parallel processing. More specifically, the present invention provides the following demodulator, and so on.
According to one aspect of the invention, the demodulator comprises:
an analog quadrature detector, responsive to a quadrature-modulated IF signal, to carry out an analog quadrature detection by the use of a predicted carrier frequency having a frequency substantially equal to an actual carrier frequency, and to output first and second quadrature-detected signals that are orthogonal to each other;
first and second A/D converters, responsive to the first and second quadrature-detected signals, to carry out A/D-conversion therefor at a rate two or more times a modulation speed, respectively, and to output first and second serial signals;
first and second serial-parallel converters to convert the first and second serial signals into first and second sets of parallel signals, respectively, each of the first and second sets of parallel signals comprising a plurality of signals with the same data rate as the modulation speed;
a first parallel FIR filter to serve as a roll-off filter which parallelly filters the first set of parallel signals at the modulation speed to output a first pair of two filtered signals; and
a second parallel FIR filter to serve as a roll-off filter which parallelly filters the second set of parallel signals at the modulation speed to output a second pair of two filtered signals.
According to another aspect of the invention, the demodulator comprises:
an analog detector, responsive to a quadrature-modulated first IF signal, to carry out a detection by the use of a predetermined frequency whose difference from a predicted carrier frequency is a modulation speed, the predicted carrier frequency having a frequency substantially equal to an actual carrier frequency, the analog detector outputting a second IF signal having the modulation speed as a pseudo-carrier frequency;
an A/D converter, responsive to the second IF signal, to carry out A/D-conversion therefor at four times the modulation speed, and to output a serial signal;
a quadrature detector, responsive to the serial signal, to carry out quadrature-detection, and to output first and second sets of parallel signals, each of the first and second sets of parallel signals comprising a plurality of signals having the same data rates as the modulation speed;
a first parallel FIR filter to function as a roll-off filter which parallelly filters the first set of parallel signals at the modulation speed to output a first pair of two filtered signals; and
a second parallel FIR filter to function as a roll-off filter which parallelly filters the second set of parallel signals at the modulation speed to output a second pair of two filtered signals.
For example, the first and second parallel FIR filters may have any of the following first to third parallel FIR filters in a case where the A/D conversion is carried out at two times the modulation speed. The first to third parallel FIR filters are suited to operate as a parallel roll-off filter which, in response to a pair of an odd-numbered data signal and an even-numbered data signal obtained by S/P-converting the serial data signal, to output a pair of a filtered odd-numbered data signal and a filtered even-numbered data signal.
According to one aspect of the invention, the first parallel FIR filter comprises: first to sixth delay circuits; first to tenth multipliers for which first to tenth multiplication coefficients are defined, respectively; and first to sixth adders; wherein:
the first to sixth delay circuits having predetermined times as their delay times, respectively;
the first, fifth, sixth and tenth multiplication coefficients are equal to each other;
the second, fourth, seventh and ninth multiplication coefficients are equal to each other;
the third and eighth multiplication coefficients are equal to each other;
the first and fourth delay circuits receive the odd-numbered data signal and the even-numbered data signal, respectively;
the second and fifth delay circuits receive outputs of the first and fourth delay circuits, respectively;
the third and sixth delay circuits receive outputs of the second and fifth delay circuits, respectively;
the first and second multipliers receive an output of the first delay circuit;
the third and fourth multipliers receive an output of the second delay circuit;
the fifth multiplier receives an output of the third delay circuit;
the sixth multiplier receives an output of the fourth delay circuit;
the seventh and eighth multipliers receive an output of the fifth delay circuit;
the ninth and tenth multipliers receive an output of the sixth delay circuit;
the first adder receives outputs of the first, third and fifth multipliers;
the second adder receives outputs of the second and fourth multipliers;
the third adder receives outputs of the sixth, eighth and tenth multipliers;
the fourth adder receives outputs of the seventh and ninth multipliers;
the fifth adder receives outputs of the first and fourth adders and produces, as an output of itself, the filtered odd-numbered data signal; and
the sixth adder receives outputs of the second and third adders and produces, as an output of itself, the filtered even-numbered data signal.
According to another aspect of the invention, the second parallel FIR filter, each of said first and second parallel FIR filters, comprises: first to sixth delay circuits; first to sixth multipliers for which first to sixth multiplication coefficients are defined, respectively; and first to eighth adders; wherein:
the first to sixth delay circuits having predetermined times as their delay times, respectively;
the first and fourth multiplication coefficients are equal to each other;
the second and fifth multiplication coefficients are equal to each other;
the third and sixth multiplication coefficients are equal to each other;
the first and fourth delay circuits receive the odd-numbered data signal and the even-numbered data signal, respectively;
the second and fifth delay circuits receive outputs of the first and fourth delay circuits, respectively;
the third and sixth delay circuits receive outputs of the second and fifth delay circuits, respectively;
the first adder receives outputs of the first and third delay circuits;
the second adder receives outputs of the first and second delay circuits;
the third adder receives outputs of the fourth and sixth delay circuits;
the fourth adder receives outputs of the fifth and sixth delay circuits;
the first multiplier receives an output of the first adder;
the second multiplier receives an output of the second adder;
the third multiplier receives an output of the second delay circuit;
the fourth multiplier receives an output of the third adder;
the fifth multiplier receives an output of the fourth adder;
the sixth-multiplier receives an output of the fifth delay circuit;
the fifth adder receives outputs of the first and third multipliers;
the sixth adder receives outputs of the fourth and sixth multipliers;
the seventh adder receives outputs of the fifth adder and the fifth multiplier and produces, as an output of itself, the filtered odd-numbered data signal; and
the eighth adder receives outputs of the sixth adder and the second multiplier and produces, as an output of itself, the filtered even-numbered data signal.
According to a further aspect of the invention, the third parallel FIR filter, each of said first and second parallel FIR filters, comprises: first to sixth delay circuits; first to eighth multipliers for which first to eighth multiplication coefficients are defined, respectively; and first to sixth adders; wherein:
the first to sixth delay circuits having predetermined times as their delay times, respectively;
the first, fourth, fifth and eighth multiplication coefficients are equal to each other;
the second, third, sixth and seventh multiplication coefficient are equal to each other;
the first and fourth delay circuits receive the odd-numbered data signal and the even-numbered data signal, respectively;
the second and fifth delay circuit receive outputs of the first and fourth delay circuits, respectively;
the third and sixth delay circuits receive outputs of the second and fifth delay circuits, respectively;
the first multiplier receives an output of the first delay circuit;
the second and third multipliers receive an output of the second delay circuit;
the fourth multiplier receives an output of the third delay circuit;
the fifth and sixth multipliers receive an output of the fifth delay circuit;
the seventh and eighth multipliers receive an output of the sixth delay circuit;
the first adder receives outputs of the first and third multipliers;
the second adder receives outputs of the second and fourth multipliers;
the third adder receives outputs of the fifth and seventh multipliers;
the fourth adder receives outputs of the sixth and eighth multipliers;
the fifth adder receives outputs of the second and third adders and produces, as an output of itself, the filtered odd-numbered data; and
the sixth adder receives outputs of the first and fourth adders and produces, as an output of itself, the filtered even-numbered data signal.